? semiconductor components industries, llc, 2002 january, 2002 rev. 7 1 publication order number: mc10125/d mc10125 quad mecl to ttl translator the mc10125 is a quad translator for interfacing data and control signals between the mecl section and saturated logic sections of digital systems. the mc10125 incorporates differential inputs and schottky ttl atotem poleo outputs. differential inputs allow for use as an inverting/ noninverting translator or as a differential line receiver. the v bb reference voltage is available on pin 1 for use in singleended input biasing. the outputs of the mc10125 go to a low logic level whenever the inputs are left floating. power supply requirements are ground, +5.0 volts and 5.2 volts. propagation delay of the mc10125 is typically 4.5 ns. the mc10125 has fanout of 10 ttl loads. the dc levels are mecl 10,000 in and schottky ttl, or ttl out. this device has an input common mode noise rejection of 1.0 volt. an advantage of this device is that mecl level information can be received, via balanced twisted pair lines, in the ttl equipment. this isolates the mecl logic from the noisy ttl environment. this device is useful in computers, instrumentation, peripheral controllers, test equipment and digital communications systems. ? p d = 380 mw typ/pkg (no load) ? t pd = 4.5 ns typ (50% to + 1.5 vdc out) ? t r , t f = 2.5 ns typ (1.0 v to 2.0 v) logic diagram 4 3 2 5 7 6 12 11 10 13 15 14 1 v bb * *v bb to be used to supply bias to the mc10125 only and bypassed (when used) with 0.01 m f to 0.1 m f capacitor to ground (0 v). v bb can source < 1.0 ma. when the input pin with the bubble goes positive, the output goes negative. gnd = pin 16 v cc (+5.0vdc) = pin 9 v ee (-5.2vdc) = pin 8 dip pin assignment v bb a in a in a out b out b in b in v ee gnd d in d in d out c out c in c in v cc 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 pin assignment is for dualinline package. for plcc pin assignment, see the pin conversion tables on page 18 of the on semiconductor mecl data book (dl122/d). http://onsemi.com device package shipping ordering information mc10125l cdip16 25 units / rail mc10125p pdip16 25 units / rail mc10125fn plcc20 46 units / rail marking diagrams 1 16 a = assembly location wl = wafer lot yy = year ww = work week cdip16 l suffix case 620 mc10125l awlyyww pdip16 p suffix case 648 plcc20 fn suffix case 775 10125 awlyyww 1 1 16 mc10125p awlyyww
mc10125 http://onsemi.com 2 electrical characteristics test limits pin under 30 c +25 c +85 c characteristic symbol u n d er test min max min typ max min max unit negative power supply drain current i e 8 44 40 44 madc positive power supply i cch 9 52 52 52 madc os e o e su y drain current i ccl 9 39 39 39 madc input current i inh 1 2 180 115 115 m adc input leakage current i cbo 2 1.5 1.0 1.0 m adc high output voltage v oh 4 2.5 2.5 2.5 vdc low output voltage v ol 4 0.5 0.5 0.5 vdc high threshold voltage v oha 4 2.5 2.5 2.5 vdc low threshold voltage v ola 4 0.5 0.5 0.5 vdc indeterminate input v ols1 4 0.5 0.5 0.5 vdc de e a e u protection tests v ols2 4 0.5 0.5 0.5 vdc short circuit current i os 4 40 100 40 100 40 100 madc reference voltage v bb 1 1.420 1.280 1.350 1.230 1.295 1.150 vdc common mode rejection tests v oh 4 4 2.5 2.5 2.5 2.5 2.5 2.5 vdc v ol 4 4 0.5 0.5 0.5 0.5 0.5 0.5 vdc switching times (50 w load) ns propagation delay (50% to +1.5vdc) t 6+5 t 65+ t 2+4 t 24+ 5 5 4 4 1.0 1.0 1.0 1.0 6.0 6.0 6.0 6.0 1.0 1.0 1.0 1.0 4.5 4.5 4.5 4.5 6.0 6.0 6.0 6.0 1.0 1.0 1.0 1.0 6.0 6.0 6.0 6.0 rise time (+1.0v to 2.0v) t 4+ 4 3.3 3.3 3.3 fall time (+1.0v to 2.0v) t 4 4 3.3 3.3 3.3 1. individually test each output, apply v ihmax to pin under test.
mc10125 http://onsemi.com 3 electrical characteristics (continued) test voltage values (volts) @ test temperature v ihmax v ilmin v ihamin v ilamax v ihh v ilh 30 c 0.890 1.890 1.205 1.500 +0.110 0.890 +25 c 0.810 1.850 1.105 1.475 +0.190 0.850 +85 c 0.700 1.825 1.035 1.440 +0.300 0.825 pin under test voltage applied to pins listed below otpt characteristic symbol under test v ihmax v ilmin v ihamin v ilamax v ihh v ilh gnd output condition negative power supply drain current i e 8 16 positive power supply i cch 9 2,6,10,14 16 os e o e su y drain current i ccl 9 2,6,10,14 16 input current i inh 1 2 2,6,10,14 16 input leakage current i cbo 2 16 high output voltage v oh 4 2,6,10,14 16 2.0ma low output voltage v ol 4 2,6,10,14 16 20ma high threshold voltage v oha 4 6,10,14 2 16 2.0ma low threshold voltage v ola 4 6,10,14 2 16 20ma indeterminate input v ols1 4 16 20ma de e a e u protection tests v ols2 4 16 20ma short circuit current i os 4 2,6,10,14 4, 16 reference voltage v bb 1 2,6,10,14 common mode rejection tests v oh 4 4 3 2 16 16 2.0ma 2.0ma v ol 4 4 2 3 16 16 20ma 20ma switching times (50 w load) pulse in pulse out c l (pf) propagation delay (50% to +1.5vdc) t 6+5 t 65+ t 2+4 t 24+ 5 5 4 4 6 6 2 2 5 5 4 4 25 25 25 25 16 16 16 16 rise time(+1.0v to 2.0v) t 4+ 4 2 4 25 16 fall time (+1.0v to 2.0v) t 4 4 2 4 25 16 1. individually test each output, apply v ihmax to pin under test.
mc10125 http://onsemi.com 4 electrical characteristics (continued) test voltage values (volts) @ test temperature v ihh v ilh v bb v cc v ee 30 c 1.890 2.890 from +5.0 5.2 +25 c 1.810 2.850 f rom pin +5.0 5.2 +85 c 1.700 2.825 pin 1 +5.0 5.2 pin under test voltage applied to pins listed below otpt characteristic symbol under test v ihh v ilh v bb v cc v ee gnd output condition negative power supply drain current i e 8 3,7,11,15 9 8 16 positive power supply i cch 9 3,7,11,15 9 8 16 os e o e su y drain current i ccl 9 3,7,11,15 9 8 16 input current i inh 1 2 3,7,11,15 9 8 16 input leakage current i cbo 2 3,7,11,15 9 2,6,8,10,14 16 high output voltage v oh 4 3,7,11,15 9 8 16 2.0ma low output voltage v ol 4 3,7,11,15 9 8 16 20ma high threshold voltage v oha 4 3,7,11,15 9 8 16 2.0ma low threshold voltage v ola 4 3,7,11,15 9 8 16 20ma indeterminate input protection tests v ols1 4 9 2,3,6,7,8, 10,11,14,15 16 20ma v ols2 4 9 8 16 20ma short circuit current i os 4 3,7,11,15 9 8 4, 16 reference voltage v bb 1 3,7,11,15 common mode rejection tests v oh 4 4 3 2 9 9 8 8 16 16 2.0ma 2.0ma v ol 4 4 2 3 9 9 8 8 16 16 20ma 20ma switching times (50 w load) propagation delay (50% to +1.5vdc) t 6+5 t 65+ t 2+4 t 24+ 5 5 4 4 3,7,11,15 3,7,11,15 3,7,11,15 3,7,11,15 9 9 9 9 8 8 8 8 16 16 16 16 rise time (+1.0v to 2.0v) t 4+ 4 3,7,11,15 9 8 16 fall time (+1.0v to 2.0v) t 4 4 3,7,11,15 9 8 16 1. individually test each output, apply v ihmax to pin under test. each mecl 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibr ium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is ma intained. outputs are terminated through a 50-ohm resistor to 2.0 volts. test procedures are shown for only one gate. the other gates are tested in the same manner.
mc10125 http://onsemi.com 5 50ohm termination to ground located in each scope channel input. all input and output cables to the scope are equal lengths of 50ohm coaxial cable. wire length should be < 1/4 inch from tp in to input pin and tp out to output pin. c l = 25 pf, including test fixture one input from each gate must be tied to v bb (pin 1) during testing. 4 3 2 5 7 6 12 11 10 13 15 14 1 v bb v out coax 16 8 0.1 m f -5.2 vdc v ee 0.1 m f pulse generator coax v in input v cc +5.0 vdc input pulse t+ = t- = 2.0 0.2 ns (20 to 80%) 450 c l 0.1 m f -1.69 vdc switching time test circuit
mc10125 http://onsemi.com 6 package dimensions plcc20 fn suffix plastic plcc package case 77502 issue c notes: 1. datums -l-, -m-, and -n- determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). m n l y brk w v d d s l-m m 0.007 (0.180) n s t s l-m m 0.007 (0.180) n s t s l-m s 0.010 (0.250) n s t x g1 b u z view dd 20 1 s l-m m 0.007 (0.180) n s t s l-m m 0.007 (0.180) n s t s l-m s 0.010 (0.250) n s t c g view s e j r z a 0.004 (0.100) t seating plane s l-m m 0.007 (0.180) n s t s l-m m 0.007 (0.180) n s t h view s k k1 f g1 dim min max min max millimeters inches a 0.385 0.395 9.78 10.03 b 0.385 0.395 9.78 10.03 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 --- 0.51 --- k 0.025 --- 0.64 --- r 0.350 0.356 8.89 9.04 u 0.350 0.356 8.89 9.04 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y --- 0.020 --- 0.50 z 2 10 2 10 g1 0.310 0.330 7.88 8.38 k1 0.040 --- 1.02 ---
mc10125 http://onsemi.com 7 package dimensions cdip16 l suffix ceramic dip package case 62010 issue t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension f may narrow to 0.76 (0.030) where the lead enters the ceramic body. a b t f e g n k c seating plane 16 pl d s a m 0.25 (0.010) t 16 pl j s b m 0.25 (0.010) t m l dim min max min max millimeters inches a 0.750 0.785 19.05 19.93 b 0.240 0.295 6.10 7.49 c --- 0.200 --- 5.08 d 0.015 0.020 0.39 0.50 e 0.050 bsc 1.27 bsc f 0.055 0.065 1.40 1.65 g 0.100 bsc 2.54 bsc h 0.008 0.015 0.21 0.38 k 0.125 0.170 3.18 4.31 l 0.300 bsc 7.62 bsc m 0 15 0 15 n 0.020 0.040 0.51 1.01 16 9 18 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 pdip16 p suffix plastic dip package case 64808 issue r
mc10125 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10125/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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